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Preliminary W742C810 4-BIT MICROCONTROLLER
Table of Contents1. GENERAL DESCRIPTION ..........................................................................................................................3 2. FEATURES..................................................................................................................................................3 3. PIN CONFIGURATION ................................................................................................................................4 4. PIN DESCRIPTION......................................................................................................................................5 4.1 Pad List ..................................................................................................................................................6 5. BLOCK DIAGRAM .......................................................................................................................................8 6. FUNCTIONAL DESCRIPTION ....................................................................................................................9 6.1 Program Counter (PC) ...........................................................................................................................9 6.2 Stack Register (STACK) ........................................................................................................................9 6.3 Program Memory (ROM) .......................................................................................................................9 6.3.1 ROM Page Register (ROMPR) ................................................................................................10 6.4 Data Memory (RAM)............................................................................................................................10 6.4.1 Architecture ..............................................................................................................................10 6.4.2 Page Register (PAGE) .............................................................................................................11 6.4.3 WR Page Register (WRP) .......................................................................................................12 6.4.4 Data Bank Register (DBKR).....................................................................................................12 6.5 Accumulator (ACC) ..............................................................................................................................13 6.6 Arithmetic and Logic Unit (ALU)...........................................................................................................13 6.7 Main Oscillator......................................................................................................................................13 6.8 Sub-Oscillator.......................................................................................................................................13 6.9 Dividers ................................................................................................................................................13 6.10 Dual-clock operation...........................................................................................................................14 6.11 Watchdog Timer (WDT).....................................................................................................................15 6.12 Timer/Counter ....................................................................................................................................15 6.12.1 Timer 0 (TM0).........................................................................................................................15 6.12.2 Timer 1 (TM1).........................................................................................................................16 6.12.3 Mode Register 0 (MR0) ..........................................................................................................17 6.12.4 Mode Register 1 (MR1) ..........................................................................................................17 6.13 Interrupts ............................................................................................................................................18 6.14 Stop Mode Operation.........................................................................................................................19 6.14.1 Stop Mode Wake-up Enable Flag for RC Port (SEF).............................................................19
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
6.15 Hold Mode Operation .........................................................................................................................19 6.15.1 Hold Mode Release Enable Flag (HEF) .................................................................................20 6.15.2 Interrupt Enable Flag (IEF) .....................................................................................................21 6.15.3 Port Enable Flag (PEF) ..........................................................................................................21 6.15.4 Hold Mode Release Condition Flag (HCF) .............................................................................22 6.15.5 Event Flag (EVF)....................................................................................................................22 6.16 Reset Function ...................................................................................................................................23 6.17 Input/Output Ports RA, RB & RD .......................................................................................................23 6.17.1 Port Mode 0 Register (PM0)...................................................................................................24 6.17.2 Port Mode 1 Register (PM1)...................................................................................................24 6.17.3 Port Mode 2 Register (PM2)...................................................................................................25 6.17.4 Port Mode 5 Register (PM5)...................................................................................................25 6.18 Input Ports RC....................................................................................................................................25 6.18.1 Port Status Register 0 (PSR0) ...............................................................................................26 6.19 Output Port RE & RF .........................................................................................................................27 6.20 DTMF Output Pin (DTMF)..................................................................................................................27 6.20.1 DTMF register.........................................................................................................................28 6.20.2 Dual Tone Control Register (DTCR).......................................................................................28 6.21 MFP Output Pin (MFP).......................................................................................................................28 6.22 LCD Controller/Driver.........................................................................................................................30 6.22.1 LCD RAM addressing method................................................................................................31 6.22.2 The output waveforms for the LCD driving mode ...................................................................31 7. ABSOLUTE MAXIMUM RATINGS ............................................................................................................33 8. DC CHARACTERISTICS...........................................................................................................................33 9. AC CHARACTERISTICS...........................................................................................................................34 10. INSTRUCTION SET TABLE ....................................................................................................................35 11. PACKAGE DIMENSIONS........................................................................................................................41
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Preliminary W742C810
1. GENERAL DESCRIPTION
The W742C810 is a high-performance 4-bit microcontroller (C) that provides an LCD driver. The device contains a 4-bit ALU, two 8-bit timers, two dividers (for two oscillators) in dual-clock operation, a 40 x 4 LCD driver, six 4-bit I/O ports (including 1 output port for LED driving), and one channel DTMF generator. There are also five interrupt sources and 8-level subroutine nesting for interrupt applications. The W742C810 operates on very low current and has one power reduction mode, that is the dual-clock slow operation, which helps to minimize power dissipation.
2. FEATURES
* Operating voltage: 2.4V-3.6V * Dual-clock operation * Main oscillator
- Connect to 3.58 MHz crystal only
* Sub-oscillator *
*
*
*
*
*
- Connect to 32768 Hz crystal only Memory - 8192 x 16 bit program ROM (including 32K x 4 bit look-up table) - 1024 x 4 bit data RAM (including 16 nibbles x 16 pages working registers) - 40 x 4 LCD data RAM 24 input/output pins - Port for input only: 1 ports/4 pins - Input/output ports: 3 ports/12 pins - High sink current output port for LED driving: 1 port /4 pins - Port for output only: 1 port/ 4 pins Power-down mode - Hold function: no operation (main oscillator and sub-oscillator still operate) - Stop function: no operation (only main oscillator stops but sub-oscillator still operates) - Dual-clock slow mode: system is operated by the sub-oscillator (FOSC = Fs and Fm is stopped) Five types of interrupts - Four internal interrupts (Divider0, Divider1, Timer 0, Timer 1) - One external interrupt (RC Port) LCD driver output - 40 segments x 4 commons - 1/4 duty 1/3 bias driving mode - Clock source should be the sub-oscillator clock in the dual-clock operation mode MFP output pin - Output is software selectable as modulating or nonmodulating frequency - Works as frequency output specified by Timer 1
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
*
DTMF output pin Two built-in 14-bit frequency dividers - Divider0: the clock source is the output of the main oscillator - Divider1: the clock source is the output of the sub-oscillator
- Output is one channel Dual Tone Multi-frequency signal for dialling
*
*
Two built-in 8-bit programmable countdown timers - Timer 0: one of two internal clock frequencies (FOSC/4 or FOSC/1024) can be selected - Timer 1: with auto-reload function, and one of three internal clock frequencies (FOSC, FOSC/64 or Fs) can be selected by MR1 register; the specified frequency can be delivered to MFP pin Built-in 18/15-bit watchdog timer selectable for system reset; enable the watch dog timer or not is determined by code option Powerful instruction set: 131 instructions 8-level subroutine (include interrupt) nesting
* * *
3. PIN CONFIGURATION
X X DXO XO V RT I UV I UDDD EMNT DNT HHD NNNN CCCCS F11D2 2 1 21
V D D 2
C O M 0
C O M 1
C O M 2
C O M 3
S E G 3 9
S E G 3 8
S E G 3 7
S E G 3 6
S E G 3 5
S E G 3 4
S E G 3NNNN 3CCCC
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC MFP RA0 RA1 RA2 RA3 RB0 RB1 RB2 RB3 RC0 RC1 RC2 RC3 RD0 RD1 RD2 RD3 RE0 NC 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 1 234567 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 NC SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14
NNNNR RRRR RRVS SS CCCCE EEF F FFSE EE 1 23 0 1 23 SGGG 012
S E G 3
S E G 4
S E G 5
S E G 6
S E G 7
S E G 8
S E G 9
S E G 1 0
S E G 1 1
S E G 1 2
SNNN N ECCC C G 1 3
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Preliminary W742C810
4. PIN DESCRIPTION
SYMBOL XIN2 XOUT2 XIN1 XOUT1 RA0-RA3 RB0-RB3 RC0-RC3 RD0-RD3 RE0-RE3 RF0-RF3 MFP DTMF
RES
I/O I O I O I/O I/O I I/O O O O O I O O I I I I
FUNCTION Input pin for sub-oscillator. Connected to 32.768 Khz crystal only. Output pin for sub-oscillator with internal oscillation capacitor. Connected to 32.768 Khz crystal only. Input pin for main-oscillator. Connected to 3.58MHz crystal to generate system clock. Output pin for main-oscillator. Connected to 3.58MHz crystal to generate system clock. Input/Output port. Input/output mode specified by port mode 1 register (PM1). Input/Output port. Input/output mode specified by port mode 2 register (PM2). 4-bit port for input only. Each pin has an independent interrupt capability. Input/Output port Input/Output mode specified by port mode 5 register (PM5) Output port only. With high sink current capacity for the LED application. Output port only. Output pin only. This pin can output modulating or nonmodulating frequency, or Timer 1 clock output specified by mode register 1 (MR1). This pin can output dual-tone multifrequency signal for dialling. System reset pin with pull-high resistor. LCD segment output pins. LCD common signal output pins. Connection terminals for voltage doubler (halver) capacitor. Positive (+) supply voltage terminal. Refer to Functional Description. Positive power supply (+). Negative power supply (-).
SEG0SEG39 COM0COM3 DH1, DH2 VDD1 VDD2 VDD VSS
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
4.1 Pad List
** Shrink factor: 1.000000; Date: 1997/12/31; Time: 14:46:10 ** Window: (xl = -1410.00, yl = -1595.00), (xh = 1410.00, yh = 1595.00) ** Windows size: width = 2820.00, length = 3190.00 PAD NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 PAD NAME RE1 RE2 RE3 RF0 RF1 RF2 RF3 VSS SEG<0> SEG<1> SEG<2> SEG<3> SEG<4> SEG<5> SEG<6> SEG<7> SEG<8> SEG<9> SEG<10> SEG<11> SEG<12> SEG<13> SEG<14> SEG<15> SEG<16> SEG<17> SEG<18> SEG<19> SEG<20> SEG<21> PIN NAME 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 31 32 33 34 35 36 37 38 X -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1302.45 -1025.28 -895.28 -765.28 -635.28 -505.28 -375.28 -251.28 Y 1336.70 1205.53 1075.53 944.00 817.58 693.58 569.58 407.95 283.95 159.95 35.95 -88.05 -212.05 -336.05 -460.05 -584.05 -708.05 -832.05 -956.38 -1086.40 -1216.40 -1350.40 -1486.30 -1489.60 -1489.60 -1489.60 -1489.60 -1489.60 -1489.60 -1489.60
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Preliminary W742C810
Pad List, continued
PAD NO. 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65
PAD NAME SEG<22> SEG<23> SEG<24> SEG<25> SEG<26> SEG<27> SEG<28> SEG<29> SEG<30> SEG<31> SEG<32> SEG<33> SEG<34> SEG<35> SEG<36> SEG<37> SEG<38> SEG<39> COM<2> COM<1> COM<0> VDD2 VDD1 DH2 DH1 XOUT2 XIN2 VDD XOUT1 XIN1 DTMF RES MFP RA0
PIN NAME 39 40 41 42 43 44 45 46 47 48 49 55 56 57 58 59 60 61 63 64 65 66 67 6 69 70 71 72 73 74 75 76 82 83
X -127.28 -3.28 120.73 244.73 368.73 498.73 628.73 758.73 888.73 1018.73 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1301.23 1024.38 894.38
Y -1489.60 -1489.60 -1489.60 -1489.60 -1489.60 -1489.60 -1489.60 -1489.60 -1489.60 -1489.60 -1486.30 -1356.30 -1222.30 -1100.30 -970.30 -840.30 -716.30 -592.30 -319.90 -179.10 -38.30 118.90 263.55 411.73 535.73 659.73 783.73 907.73 1075.50 1205.50 1336.68 1466.70 1470.00 1470.00
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Preliminary W742C810
Pad List, ontinued
PAD NO. 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81
PAD NAME RA1 RA2 RA3 RB0 RB1 RB2 RB3 RC0 RC1 RC2 RC3 RD0 RD1 RD2 RD3 RE0
PIN NAME 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
X 764.38 634.38 504.38 374.38 250.38 126.38 2.38 -121.63 -245.63 -369.63 -499.63 -629.63 -759.63 -889.63 -1019.63 -1302.45
Y 1470.00 1470.00 1470.00 1470.00 1470.00 1470.00 1470.00 1470.00 1470.00 1470.00 1470.00 1470.00 1470.00 1470.00 1470.00 1466.70
5. BLOCK DIAGRAM
SEG0~SEG39 COM0~COM4 VDD1~VDD2,DH1~2
RAM (1024*4)
LCD
DRIVER
PORT RA ROM (8192*16)
(look_up table 32K*4)
+1(+2)
RA0-3 RB0-3 RC0-3 RD0-3 RE0-3
ACC
PORT RB PORT RC PORT RD PORT RE PORT RF DTMF Generator
ALU
PC
Central Control Unit
IEF HEF EVF SCR MR1 PEF SEF PR PM0
RF0-3 DTMF
STACK (8 Levels)
HCF PSR0 MR0
.
.
.
SEL
MUL
MFP
Timer 0 (8 Bit)
Timer 1 (8 Bit)
Modulation Frequency Pulse
Divider 1 (12/14 Bit) VDD VSS
Watch Dog Timer (4 Bit)
Divider 0 (14 Bit)
Timing Generator RES
XIN2 XOUT2 XIN1 XOUT1
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Preliminary W742C810
6. FUNCTIONAL DESCRIPTION
6.1 Program Counter (PC)
Organized as a 13-bit binary counter (PC0 to PC12), the program counter generates the addresses of the 8192 x 16 on-chip ROM containing the program instruction words. Before the jump or subroutine call instructions are to be executed, the destination ROM page must be determined first. The confirmation of the ROM page can be done by executing the MOV ROMPR, #I or MOV ROMPR, R instruction. When the interrupt or initial reset conditions are to be executed, the corresponding address will be loaded into the program counter directly. The format used is shown below. Table 1 Vector address and interrupt priority ITEM Initial Reset INT 0 (Divider0) INT 1 (Timer 0) INT 2 (Port RC) INT 3 (Divider1) INT 4 (Timer 1) JP Instruction Subroutine Call ADDRESS 0000H 0004H 0008H 000CH 0014H 0020H XXXXH XXXXH INTERRUPT PRIORITY 1st 2nd 3rd 4th 5th -
6.2 Stack Register (STACK)
The stack register is organized as 13 bits x 8 levels (first-in, last-out). When either a call subroutine or an interrupt is executed, the program counter will be pushed onto the stack register automatically. At the end of a call subroutine or an interrupt service subroutine, the RTN instruction must be executed to pop the contents of the stack register into the program counter. When the stack register is pushed over the eighth level, the contents of the first level will be lost. In other words, the stack register is always eight levels deep.
6.3 Program Memory (ROM)
The read-only memory (ROM) is used to store program codes; the look-up table is arranged as 32768 x4 bits. The program ROM is divided into four pages; the size of each page is 2048 x 16 bits. Total ROM size is therefore 8192 x 16 bits. Before the jump or subroutine call instructions are to be executed, the destination ROM page must be determined first. The ROM page can be selected by executing the MOV ROMPR, #I or MOV ROMPR, R instruction. However, the branch decision instructions (e.g. JB0, SKB0, JZ, JC, ...) must jump to the same ROM page which the branch decision instructions are located in. The whole ROM range can store both instruction codes and the look-up table. Each look-up table element is composed of 4 bits, so the look-up table can be addressed up to 32768 elements. Instruction MOVC R is used to read the look-up table content and transfer table data to the RAM. But before reading the addressed look-up table content, the content of the look-up table pointer (TAB) must be determined first. The address of the look-up table element is allocated by the content of TAB. The MOV TAB0 (TAB1, TAB2, TAB3), R instructions are used to allocate the address of the wanted look-up table element. The TAB0 register stores the LSB 4 bits of the look-up table address. The organization of the program memory is shown in Figure 6-1. Publication Release Date: May 1999 Revision A1
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Preliminary W742C810
16 bits 0000H : 03FFH 1st page 0400H : 07FFH 0800H : 2nd page 0BFFH 0C00H : 0FFFH 1000H : 3rd page 13FFH 1400H : 17FFH 1800H : 4th page 1BFFH 1C00H : 1FFFH
Look-up Table address: 0000H : 0FFFH
Each element (4 bits) of the look-up table
Look-up Table address: 1000H : 1FFFH
: :
Look-up Table address: 2000H : 2FFFH
Look-up Table address: 3000H : 3FFFH
Look-up Table address: 4000H : 4FFFH Look-up Table address: 5000H : 5FFFH
Look-up Table address: 6000H : 6FFFH Look-up Table address: 7000H : 7FFFH
8192 * 16 bits
Figure 6-1 Program Memory Organization
6.3.1 ROM Page Register (ROMPR) The ROM page register is organized as a 4-bit binary register. The bit descriptions are as follows: 3 ROMPR
Note: R/W means read/write available.
2
1 R/W
0 R/W
Bit 3 & Bit 2 is reserved. Bit 1, Bit 0 ROM page preselect bits: 00 = ROM page 0 (0000H - 07FFH) 01 = ROM page 1 (0800H - 0FFFH) 10 = ROM page 2 (1000H - 17FFH) 11 = ROM page 3 (1800H - 1FFFH)
6.4 Data Memory (RAM)
6.4.1 Architecture The static data memory (RAM) used to store data is arranged as 1024 x 4 bits. The data RAM is divided into eight banks; each bank has 128 x 4 bits. Executing the MOV DBKR,WR or MOV DBKR,#I instruction can determine which data bank is used. The data memory can be addressed - 10 -
Preliminary W742C810
directly or indirectly. However, the data bank must be confirmed first; the page in the data bank will be done in the indirect addressing mode, too. In indirect addressing mode, each data bank will be divided into eight pages. Before the data memory is addressed indirectly, the page which the data memory is located in must be confirmed. The organization of the data memory is shown in Figure 62.
4 bits 000H : 07FH 080H : 0FFH 1st data bank
(or Working Registers bank) 1st data RAM page (or 1st WR page) 2nd data RAM page (or 2nd WR page) 3rd data RAM page (or 3rd WR page) : : 8th data RAM page (or 8th WR page) 70H : 7FH 00H : 0FH 10H : 1FH 20H : 2FH
2nd data bank
(or Working Registers bank)
1024 address
: : : 380H : 3FFH 8th data bank 1024 * 4 bits
Figure 6-2 Data Memory Organization
The 1st and 2nd data bank (00H to 7FH & 80H to FFH) in the data memory can also be used as the working registers (WR). This is also divided into sixteen pages. Each page contains 16 working registers. When one page is used as WR, the others can be used as the normal data memory. The WR page can be switched by executing the MOV WRP,R or MOV WRP,#I instruction. The data memory cannot operate directly with immediate data, but the WR can do so. The relationship between data memory locations and the page register (PAGE) in indirect addressing mode is described in the next sub-section. 6.4.2 Page Register (PAGE) The page register is organized as a 4-bit binary register. The bit descriptions are as follows: 3 PAGE
Note: R/W means read/write available.
2 R/W
1 R/W
0 R/W
Bit 3 is reserved. Bit 2, Bit 1, Bit 0 Indirect addressing mode preselect bits in one data bank: 000 = Page 0 (00H - 0FH) 001 = Page 1 (10H - 1FH) 010 = Page 2 (20H - 2FH) 011 = Page 3 (30H - 3FH) 100 = Page 4 (40H - 4FH) 101 = Page 5 (50H - 5FH) 110 = Page 6 (60H - 6FH) 111 = Page 7 (70H - 7FH)
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
6.4.3 WR Page Register (WRP) The WR page register is organized as a 4-bit binary register. The bit descriptions are as follows: 3 WRP
Note: R/W means read/write available.
2 R/W
1 R/W
0 R/W
R/W
Bit 3, Bit 2, Bit 1, Bit 0 Working registers page preselect bits: 0000 = WR Page 0 (00H - 0FH) 0001 = WR Page 1 (10H - 1FH) 0010 = WR Page 2 (20H - 2FH) 0011 = WR Page 3 (30H - 3FH) 0100 = WR Page 4 (40H - 4FH) 0101 = WR Page 5 (50H - 5FH) 0110 = WR Page 6 (60H - 6FH) 0111 = WR Page 7 (70H - 7FH) 1000 = WR Page 8 (80H - 8FH) 1001 = WR Page 9 (90H - 9FH) 1010 = WR Page A (A0H - AFH) 1011 = WR Page B (B0H - BFH) 1100 = WR Page C (C0H - CFH) 1101 = WR Page D (D0H - DFH) 1110 = WR Page E (E0H - EFH) 1111 = WR Page F (F0H - FFH) 6.4.4 Data Bank Register (DBKR) The data bank register is organized as a 4-bit binary register. The bit descriptions are as follows: 3 DBKR
Note: R/W means read/write available.
2 R/W
1 R/W
0 R/W
Bit 3 is reserved. Bit 2, Bit 1, Bit 0 Data memory bank preselect bits: 000 = Data bank 0 (000H - 07FH) 001 = Data bank 1 (080H - 0FFH) 010 = Data bank 2 (100H - 17FH) 011 = Data bank 3 (180H - 1FFH) 100 = Data bank 4 (200H - 27FH) 101 = Data bank 5 (280H - 2FFH) 110 = Data bank 6 (300H - 37FH) 111 = Data bank 7 (380H - 3FFH) - 12 -
Preliminary W742C810
6.5 Accumulator (ACC)
The accumulator (ACC) is a 4-bit register used to hold results from the ALU and transfer data between the memory, I/O ports, and registers.
6.6 Arithmetic and Logic Unit (ALU)
This is a circuit which performs arithmetic and logic operations. The ALU provides the following functions: * Logic operations: ANL, XRL, ORL * Branch decisions: JB0, JB1, JB2, JB3, JNZ, JZ, JC, JNC, DSKZ, DSKNZ, SKB0, SKB1, SKB2, SKB3 * Shift operations: SHRC, RRC, SHLC, RLC * Binary additions/subtractions: ADC, SBC, ADD, SUB, ADU, DEC, INC After any of the above instructions are executed, the status of the carry flag (CF) and zero flag (ZF) is stored in the internal registers. CF can be read out by executing MOV R, CF.
6.7 Main Oscillator
The W742C810 provides a crystal oscillation circuit to generate the system clock through external connections. The 3.58 MHz crystal must be connected to XIN1 and XOUT1, and a capacitor must be connected to XIN1 and VSS if an accurate frequency is needed.
XIN1 Crystal 3.58MHz XOUT1
Figure 6-3 System clock oscillator Configuration
6.8 Sub-Oscillator
The sub-oscillator is used in dual-clock operation mode. In the sub-oscillator application, only the 32768 Hz crystal can be connected to XIN2 and XOUT2, and a capacitor must be connected to XIN2 and VSS if an accurate frequency is needed. The sub-oscillator will be oscillatory continuously in STOP mode.
6.9 Dividers
Each divider is organized as a 14-bit binary up-counter designed to generate periodic interrupts. When the main oscillator starts action, the Divider0 is incremented by each clock (FOSC). When an overflow occurs, the Divider0 event flag is set to 1 (EVF.0 = 1). Then, if the Divider0 interrupt enable flag has been set (IEF.0 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.0 = 1), the hold state is terminated. The last 4-stage of the Divider0 can be reset by executing CLR DIVR0 instruction. If the main oscillator is connected to the 32768 Hz crystal, the EVF.0 will be set to 1 periodically at the period of 500 mS. If the sub-oscillator starts action, the Divider1 is incremented by each clock (Fs). When an overflow occurs, the Divider1 event flag is set to 1 (EVF.4 = 1). Then, if the Divider1 interrupt enable flag has been set (IEF.4 = 1), the interrupt is executed, while if the hold release enable flag has been set (HEF.4 = 1), the hold state is terminated. The last 4-stage of the Divider1 can be reset by executing CLR DIVR1 instruction. The same as with EVF.0, the EVF.4 is set to 1 periodically. However, there Publication Release Date: May 1999 Revision A1
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Preliminary W742C810
are two period times (125 mS & 500 mS) that can be selected by setting the SCR.3 bit. When SCR.3 = 0 (default), the 500 mS period time is selected; SCR.3 = 1, the 125 mS period time is selected.
6.10 Dual-clock operation
In the dual-clock mode, the clock source of the LCD frequency selector should be the sub-oscillator clock (32768 Hz) only. So when the STOP instruction is executing, the LCD will keep working in the dual-clock mode. In this dual-clock mode, the normal operation is performed by generating the system clock from the main-oscillator clock (Fm). The slow operation can be performed as required by generating the system clock from the sub-oscillator clock (Fs). The exchange of the normal operation and the slow operation is performed by resetting or setting the bit 0 of the System clock Control Register (SCR). If the SCR.0 is reset to 0, the clock source of the system clock generator is main-oscillator clock; if the SCR.0 is set to 1, the clock source of the system clock generator is sub-oscillator clock. In the dualclock mode, the main-oscillator can stop oscillating when the STOP instruction is executing or the SCR.1 is set to 1. When the SCR is set or reset, we must be careful in the following cases: 1. X000B X011B: we should not exchange the FOSC from Fm into Fs and disable Fm simultaneously. We can first exchange the FOSC from Fm into Fs, then disable the main-oscillator. So the order should be X000BX001BX011B. 2. X011B X000B: we should not enable Fm and exchange the FOSC from Fs into Fm simultaneously. We can first enable the main-oscillator; the 2nd step is calling a delay subroutine to wait until the main-oscillator is oscillating stably; then the last step is to exchange the FOSC from Fs into Fm. So the order should be X011BX001Bdelay the Fm oscillating stably timeX000B. We must remember that the X010B state is inhibitive, because it will induce the system shutdown. The organization of the dual-clock operation mode is shown in Figure 6-4.
HOLD SCR.0 XIN1 XOUT1 SCR.1 Fm Fs enable/disable STOP
Main Oscillator
Fosc
System Clock Generator Divider 0 LCD Frequency Selector
T1 T2 T3 T4
XIN2 XOUT2
Sub-oscillator Divider 1
F LCD
INT4 HCF.4
SCR.3(14/12 bit) SCR: System clock Control Register ( default = 00H ) Bit3 Bit2 Bit1 Bit0 0 : Fosc = Fm 1 : Fosc = Fs 0 : Fm enable 1 : Fm disable 0 : WDT input clock is Fosc/2048 1 : WDT input clock is Fosc/16384 0 : 14 bit 1 : 12 bit
Daul clock operation mode: - SCR.0 = 0, Fosc = Fm; SCR.0 = 1, Fosc = Fs - Flcd = Fs, In STOP mode LCD work continue.
Figure 6-4 Organization of the dual-clock operation mode
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Preliminary W742C810
6.11 Watchdog Timer (WDT)
The watchdog timer (WDT) is organized as a 4-bit up counter designed to prevent the program from unknown errors. When the corresponding option code bit of the WDT set to 1, the WDT is enabled, and if the WDT overflows, the chip will be reset. At initial reset, the input clock of the WDT is FOSC/2048. The input clock of the WDT can be switched to FOSC/16384 (or FOSC/2048) by setting SCR.2 to 1 (or clearing SCR.2 to 0). The contents of the WDT can be reset by the instruction CLR WDT. In normal operation, the application program must reset WDT before it overflows. A WDT overflow indicates that operation is not under control and the chip will be reset. The WDT overflow period is 1S when the system clock (FOSC) is 32 KHz and WDT clock input is FOSC/2048. When the corresponding option code bit of the WDT set to 0, the WDT function is disabled. The organization of the Divider0 and watchdog timer is shown in Figure 6-5.
Divider0
Fosc
Q1 Q2
HEF.0
S
...
EVF.0
Q
Q9
Q10 Q11 Q12 Q13 Q14
IEF.0
Hold mode release (HCF.0) Divider interrupt (INT0)
R
Option code is reset to "0" SCR.2 Disable
1. Reset 2. CLR EVF,#01H 3. CLR DIVR0
WDT
Qw1 Qw2 Qw3 Qw4
R R R R
Fosc/16384 Fosc/2048
Overflow signal
System Reset
Enable Option code is set to "1"
1. Reset 2. CLR WDT
Figure 6-5 Organization of Divider0 and watchdog timer
6.12 Timer/Counter
6.12.1 Timer 0 (TM0) Timer 0 (TM0) is a programmable 8-bit binary down-counter. The specified value can be loaded into TM0 by executing the MOV TM0L(TM0H),R instructions. When the MOV TM0L(TMOH),R instructions are executed, it will stop the TM0 down-counting (if the TM0 is down-counting) and reset the MR0.3 to 0, and the specified value can be loaded into TM0. We can then set MR0.3 to 1; this will cause the event flag 1 (EVF.1) to be reset, and the TM0 will start to count. When it decrements to FFH, Timer 0 stops operating and generates an underflow (EVF.1 = 1). Then, if the Timer 0 interrupt enable flag has been set (IEF.1 = 1), the interrupt is executed, while if the hold release enable flag 1 has been set (HEF.1 = 1), the hold state is terminated. The Timer 0 clock input can be set as FOSC/1024 or FOSC/4 by setting MR0.0 to 1 or resetting MR0.0 to 0. The default timer value is FOSC/4. The organization of Timer 0 is shown in Figure 6-6. If the Timer 0 clock input is FOSC/4: Desired Timer 0 interval = (preset value +1) x 4 x 1/ FOSC If the Timer 0 clock input is FOSC/1024: Desired Timer 0 interval = (preset value +1) x 1024 x 1/ FOSC Preset value: Decimal number of Timer 0 preset value FOSC: Clock oscillation frequency Publication Release Date: May 1999 Revision A1
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Preliminary W742C810
1. Reset 2. CLR EVF,#02H 3. Reset MR0.3 to 0 4.MOV TM0L,R or MOV TM0H,R MR0.0 Fosc/1024 Fosc/4 Enable Set MR0.3 to 1 MOV TM0H,R MOV TM0L,R 1. Reset 2. CLR EVF,#02H 3.Set MR0.3 to 1 Disable 8-Bit Binary Down Counter (Timer 0) 4 4 HEF.1 S R Hold mode release (HCF.1) Q EVF.1 IEF.1 Timer 0 interrupt (INT1)
Figure 6-6 Organization of Timer 0
6.12.2 Timer 1 (TM1) Timer 1 (TM1) is also a programmable 8-bit binary down counter, as shown in Figure 6-7. Timer 1 can be used as to output an arbitrary frequency to the MFP pin. The input clock of Timer 1 can be one of three sources: FOSC/64, FOSC or FS. The source can be selected by setting bit 0 and bit1 of mode register 1 (MR1). At initial reset, the Timer 1 clock input is FOSC. When the MOV TM1L, R or MOV TM1H,R instruction is executed, the specified data are loaded into the auto-reload buffer and the TM1 down-counting will keep going on. If the bit 3 of MR1 is set (MR1.3 = 1), the content of the autoreload buffer will be loaded into the TM1 down counter, Timer 1 starts to down count, and the event flag 7 is reset (EVF.7 = 0). When the timer decrements to FFH, it will generate an underflow (EVF.7 = 1) and be auto-reloaded with the specified data, after which it will continue to count down. Then, if interrupt enable flag 7 has been set to 1 (IEF.7 = 1), an interrupt is executed; if hold mode release enable flag 7 is set to 1 (HEF.7 = 1), the hold state is terminated. The specified frequency of Timer 1 can be delivered to the MFP output pin by programming bit2 of MR1. Bit 3 of MR1 can be used to make Timer 1 stop or start counting. In a case where Timer 1 clock input is FT: Desired Timer 1 interval = (preset value +1) / FT Desired frequency for MFP output pin = FT / (preset value + 1) / 2 (Hz) Preset value: Decimal number of Timer 1 preset value FOSC: Clock oscillation frequency
MOV TM1H,R 4 MOV TM1L,R 4 S Set MR1.3 to 1 Auto-reload buffer 8 bits 8-Bit Binary Down Counter (Timer 1) Disable Reset Set MR1.3 to 1 MR1.0 R Q EVF.7 1. Reset 2. INT7 accept 3. CLR EVF, #80H 4. Set MR1.3 to 1
Enable Fs FT
Underflow signal
2
circuit
Reset
Fosc/64 Fosc
MR1.1
MFP output pin MFP signal MR1.2
Figure 6-7 Organization of Timer 1
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Preliminary W742C810
For example, when FT equals 32768 Hz, depending on the preset value of TM1, the MFP pin will output a single tone signal in the tone frequency range from 64 Hz to 16384 Hz. The relation between the tone frequency and the preset value of TM1 is shown in the table below. Table2 The relation between the tone frequency and the preset value of TM1
3rd octave
Tone frequency TM1 preset value & MFP frequency 7CH 75H 6FH 68H 62H 5DH 58H 53H 4EH 49H 45H 41H 131.07 138.84 146.28 156.03 165.49 174.30 184.09 195.04 207.39 221.40 234.05 248.24
4th octave
Tone frequency 261.63 277.18 293.66 311.13 329.63 349.23 369.99 392.00 415.30 440.00 466.16 493.88 TM1 preset value & MFP frequency 3EH 3AH 37H 34H 31H 2EH 2BH 29H 26H 24H 22H 20H 260.06 277.69 292.57 309.13 327.68 372.36 390.09 420.10 443.81 442.81 468.11 496.48
5th octave
Tone frequency 523.25 554.37 587.33 622.25 659.26 698.46 739.99 783.99 830.61 880.00 932.23 987.77 TM1 preset value & MFP frequency 1EH 1CH 1BH 19H 18H 16H 15H 14H 13H 12H 11H 10H 528.51 564.96 585.14 630.15 655.36 712.34 744.72 780.19 819.20 862.84 910.22 963.76
C C# D
130.81 138.59 146.83 155.56 164.81 174.61 # 185.00 196.00 207.65 220.00 233.08 246.94
T O N E
D# E F F G G# A A# B
Note: Central tone is A4 (440 Hz).
6.12.3 Mode Register 0 (MR0) Mode Register 0 is organized as a 4-bit binary register (MR0.0 to MR0.3). MR0 can be used to control the operation of Timer 0. The bit descriptions are as follows: 3 MR0
Note: W means write only.
2 W
1 W
0 W
W
Bit 0 = 0 =1 Bit 3 = 0 =1
The fundamental frequency of Timer 0 is FOSC/4. The fundamental frequency of Timer 0 is FOSC/1024. Timer 0 stops down-counting. Timer 0 starts down-counting.
Bit 1 & Bit 2 are reserved
6.12.4 Mode Register 1 (MR1) Mode Register 1 is organized as a 4-bit binary register (MR1.0 to MR1.3). MR1 can be used to control the operation of Timer 1. The bit descriptions are as follows: 3 MR1
Note: W means write only.
2 W
1 W
0 W
W
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
Bit 0 = 0 The internal fundamental frequency of Timer 1 is FOSC. = 1 The internal fundamental frequency of Timer 1 is FOSC/64. Bit 1 = 0 The fundamental frequency source of Timer 1 is the internal clock. = 1 The fundamental frequency source of Timer 1 is the sub-oscillator frequency FS (32.768 KHz). Bit 2 = 0 The specified waveform of the MFP generator is delivered at the MFP pin. = 1 The specified frequency of Timer 1 is delivered at MFP pin. Bit 3 = 0 Timer 1 stops down-counting. = 1 Timer 1 starts down-counting.
6.13 Interrupts
The W742C810 provides four internal interrupt sources (Divider 0, Divider 1, Timer 0, Timer 1) and one external interrupt source (port RC). Vector addresses for each of the interrupts are located in the range of program memory (ROM) addresses 004H to 020H. The flags IEF, PEF, and EVF are used to control the interrupts. When EVF is set to "1" by hardware and the corresponding bits of IEF and PEF have been set by software, an interrupt is generated. When an interrupt occurs, all of the interrupts are inhibited until the EN INT or MOV IEF,#I instruction is invoked. The interrupts can also be disabled by executing the DIS INT instruction. When an interrupt is generated in hold mode, the hold mode will be released momentarily and interrupt subroutine will be executed. After the RTN instruction is executed in an interrupt subroutine, the C will enter hold mode again. The operation flow chart is shown in Figure 6-9. The control diagram is shown below.
EN INT Divider 0 overflow signal MOV IEF, #I S R Timer 0 underflow signal EVF.1 Q EVF.0
Initial Reset Enable
IEF.0
S R
Q
IEF.1 EVF.2 IEF.2 EVF.4 IEF.4 EVF.7 IEF.7 Interrupt Process Circuit Interrupt Vector Generator
004H 008H 00CH 014H 020H
Port RC signal change
S R
Q
Divider 1 overflow signal
S R
Q
Timer 1 underflow signal
S R
Q
Initial Reset Disable CLR EVF, #I instruction
DIS INT instruction
Figure 6-8 Interrupt event control duagram
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Preliminary W742C810
6.14 Stop Mode Operation
In stop mode, all operations of the C cease (excluding the operation of the sub-oscillator and Divider 1 and LCD driver), and MFP pin is kept to high state. The C enters stop mode when the STOP instruction is executed and exits stop mode when an external trigger is activated (by a falling signal on the RC). When the designated signal is accepted, the C awakens and executes the next instruction. To prevent erroneous execution, the NOP instruction should follow the STOP command. However, in the dual-clock slow operation mode, the STOP instruction will disable the main-oscillator; the C system is still operated by the sub-oscillator. 6.14.1 Stop Mode Wake-up Enable Flag for RC Port (SEF) The stop mode wake-up flag for port RC is organized as a 4-bit binary register (SEF.0 to SEF.3). Before port RC may be used to make the device exit the stop mode, the content of the SEF must be set first. The SEF is controlled by the MOV SEF, #I instruction. The bit descriptions are as follows: 3 SEF w 2 w 1 w 0 w
Note: W means write only.
SEF.0 = 1 SEF.1 = 1 SEF.2 = 1 SEF.3 = 1
Device will exit stop mode when falling edge signal is applied to pin RC.0 Device will exit stop mode when falling edge signal is applied to pin RC.1 Device will exit stop mode when falling edge signal is applied to pin RC.2 Device will exit stop mode when falling edge signal is applied to pin RC.3
6.15 Hold Mode Operation
In hold mode, all operations of the C cease, except for the operation of the oscillator, Timer, Divider, LCD driver, DTMF generator and MFP generator. The C enters hold mode when the HOLD instruction is executed. The hold mode can be released in one of five ways: by the action of timer 0, timer 1, divider 0, divider 1, or the RC port. Before the device enters the hold mode, the HEF, PEF, and IEF flags must be set to define the hold mode release conditions. For more details, refer to the instruction-set table and the following flow chart.
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
Divider 0, Divider 1, Timer 0, Timer 1, Signal Change at RC Port
Yes
In HOLD Mode?
No
Interrupt Enable? Yes
No
Interrupt Enable? Yes
No
IEF Flag Set? Yes Reset EVF Flag Execute Interrupt Service Routine (Note)
No
IEF Flag Set? Yes Reset EVF Flag Execute Interrupt Service Routine Yes
No
HEF Flag Set? No
(Note)
Disable interrupt
Disable interrupt
HOLD
PC <- (PC+1)
Note: The bit of EVF corresponding to the interrupt signal will be reset.
Figure 6-9 Hold Mode and Interrupt Operation Flow Chart
6.15.1 Hold Mode Release Enable Flag (HEF) The hold mode release enable flag is organized as an 8-bit binary register (HEF.0 to HEF.7). The HEF is used to control the hold mode release conditions. It is controlled by the MOV HEF, #I instruction. The bit descriptions are as follows: 7 HEF
Note: W means write only.
6
5
4 w
3
2 w
1 w
0 w
w
HEF.0 = 1 Overflow from the Divider 0 causes Hold mode to be released. HEF.1 = 1 Underflow from Timer 0 causes Hold mode to be released. HEF.2 = 1 Signal change at port RC causes Hold mode to be released.
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Preliminary W742C810
HEF.3 is reserved. HEF.4 = 1 Overflow from the Divider 1 causes Hold mode to be released. HEF.5 & HEF.6 are reserved. HEF.7 = 1 Underflow from Timer 1 causes Hold mode to be released. 6.15.2 Interrupt Enable Flag (IEF) The interrupt enable flag is organized as an 8-bit binary register (IEF.0 to IEF.7). These bits are used to control the interrupt conditions. It is controlled by the MOV IEF, #I instruction. When one of these interrupts is accepted, the corresponding bit of the event flag will be reset, but the other bits are unaffected. In interrupt subroutine, these interrupts will be disabled till the instruction MOV IEF, #I or EN INT is executed again. Otherwise, these interrupts can be disabled by executing DIS INT instruction. The bit descriptions are as follows: 7 IEF w 6 5 4 w 3 2 w 1 w 0 w
Note: W means write only.
IEF.0 = 1 Interrupt 0 is accepted by overflow from the Divider 0. IEF.1 = 1 Interrupt 1 is accepted by underflow from the Timer 0. IEF.2 = 1 Interrupt 2 is accepted by a signal change at port RC. IEF.3 is reserved. IEF.4 = 1 Interrupt 0 is accepted by overflow from the Divider 1. IEF.5 & IEF.6 are reserved. IEF.7 = 1 Interrupt 7 is accepted by underflow from Timer 1. 6.15.3 Port Enable Flag (PEF) The port enable flag is organized as a 4-bit binary register (PEF.0 to PEF.3). Before port RC may be used to release the hold mode or preform interrupt function, the content of the PEF must be set first. The PEF is controlled by the MOV PEF, #I instruction. The bit descriptions are as follows: 3 PEF w 2 w 1 w 0 w
Note: W means write only.
PEF.0: Enable/disable the signal change at pin RC.0 to release hold mode or perform interrupt. PEF.1: Enable/disable the signal change at pin RC.1 to release hold mode or perform interrupt. PEF.2: Enable/disable the signal change at pin RC.2 to release hold mode or perform interrupt. PEF.3: Enable/disable the signal change at pin RC.3 to release hold mode or perform interrupt.
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
6.15.4 Hold Mode Release Condition Flag (HCF) The hold mode release condition flag is organized as an 8-bit binary register (HCF.0 to HCF.7). It indicates by which interrupt source the hold mode has been released, and is loaded by hardware. The HCF can be read out by the MOVA R, HCFL and MOVA R, HCFH instructions. When any of the HCF bits is "1," the hold mode will be released and the HOLD instruction is invalid. The HCF can be reset by the CLR EVF or MOV HEF,#I (HEF = 0) instructions. When EVF and HEF have been reset, the corresponding bit of HCF is reset simultaneously. The bit descriptions are as follows: 7 HCF
Note: R means read only.
6
5 R
4 R
3
2 R
1 R
0 R
HCF.0 = 1 Hold mode was released by overflow from the divider 0. HCF.1 = 1 Hold mode was released by underflow from the timer 0. HCF.2 = 1 Hold mode was released by a signal change at port RC. HCF.3 is reserved. HCF.4 = 1 Hold mode was released by overflow from the divider 1. HCF.5 = 1 Hold mode was released by underflow from the timer 1. HCF.6 and HCF.7 are reserved. 6.15.5 Event Flag (EVF) The event flag is organized as an 8-bit binary register (EVF.0 to EVF.7). It is set by hardware and reset by CLR EVF,#I instruction or the occurrence of an interrupt. The bit descriptions are as follows: 7 EVF
Note: W means write only.
6
5
4 W
3
2 W
1 W
0 W
W
EVF.0 = 1 Overflow from divider 0 occurred. EVF.1 = 1 Underflow from timer 0 occurred. EVF.2 = 1 Signal change at port RC occurred. EVF.3 is reserved. EVF.4 = 1 Overflow from divider 1 occurred. EVF.5 & EVF.6 are reserved. EVF.7 = 1 Underflow from Timer 1 occurred.
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Preliminary W742C810
6.16 Reset Function
The W742C810 is reset either by a power-on reset or by using the external RES pin. The initial state of the W742C810 after the reset function is executed is described below. Program Counter (PC) TM0, TM1 MR0, MR1, PAGE registers PSR0, SCR registers IEF, HEF, HCF, PEF, EVF, SEF flags WRP, DBKR register Timer 0 input clock Timer 1 input clock MFP output DTMF output Input/output ports RA,RB, RD Output port RE & RF RA, RB & RD ports output type RC ports pull-high resistors Input clock of the watchdog timer LCD display 000H Reset Reset Reset Reset Reset FOSC/4 FOSC Low Hi-Z Input mode High CMOS type Disable FOSC/2048 OFF
Table 3 The initial state after the reset function is executed
6.17 Input/Output Ports RA, RB & RD
Port RA consists of pins RA.0 to RA.3. Port RB consists of pins RB.0 to RB.3. Port RD consists of pins RD.0 to RD.3. At initial reset, input/output ports RA, RB and RD are all in input mode. When RA, RB are used as output ports, CMOS or NMOS open drain output type can be selected by the PM0 register. But when RD is used as output port, the output type is just fixed to be CMOS output type. Each pin of port RA, RB and RD can be specified as input or output mode independently by the PM1, PM2 and PM5 registers. The MOVA R, RA or MOVA R, RB or MOVA R, RD instructions operate the input functions and the MOV RA, R or MOV RB, R or MOV RD, R operate the output functions. For more details, refer to the instruction table and Figure 6-10 and Figure 6-11.
Input/Output Pin of the RA(RB)
PM0.0(PM0.1)
DATA BUS
Output Buffer
Enable
I/O PIN RA.n(RB.n)
PM1.n (PM2.n)
MOV RA,R(MOV RB,R) instruction
Enable
MOVA R,RA(MOVA R,RB) instruction
Figure 6-10 Architecture of RA (RB) Input/Output Pins
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
Input/Output Pin of the RD
DATA BUS
Output Buffer
Enable
I/O PIN RD.n
PM5.n
MOV RD,R instruction
Enable
MOVA R,RD instruction
Figure 6-11 Architecture of RD Input/Output pins
6.17.1 Port Mode 0 Register (PM0) The port mode 0 register is organized as a 4-bit binary register (PM0.0 to PM0.3). PM0 can be used to determine the structure of the input/output ports; it is controlled by the MOV PM0, #I instruction. The bit descriptions are as follows: 3 PM0
Note: W means write only.
2 w
1 w
0 w
w
Bit 0 = 0 RA port is CMOS output type. Bit 0 = 1 RA port is NMOS open drain output type. Bit 1 = 0 RB port is CMOS output type. Bit 1 = 1 RB port is NMOS open drain output type. Bit 2 = 0 RC port pull-high resistor is disabled. Bit 2 = 1 RC port pull-high resistor is enabled. Bit 3 is reserved. 6.17.2 Port Mode 1 Register (PM1) The port mode 1 register is organized as a 4-bit binary register (PM1.0 to PM1.3). PM1 can be used to control the input/output mode of port RA. PM1 is controlled by the MOV PM1, #I instruction. The bit descriptions are as follows: 3 PM1
Note: W means write only.
2 w
1 w
0 w
w
Bit 0 = 0 RA.0 works as output pin; Bit 0 = 1 RA.0 works as input pin Bit 1 = 0 RA.1 works as output pin; Bit 1 = 1 RA.1 works as input pin Bit 2 = 0 RA.2 works as output pin; Bit 2 = 1 RA.2 works as input pin Bit 3 = 0 RA.3 works as output pin; Bit 3 = 1 RA.3 works as input pin At initial reset, port RA is input mode (PM1 = 1111B).
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Preliminary W742C810
6.17.3 Port Mode 2 Register (PM2) The port mode 2 register is organized as a 4-bit binary register (PM2.0 to PM2.3). PM2 can be used to control the input/output mode of port RB. PM2 is controlled by the MOV PM2, #I instruction. The bit descriptions are as follows: 3 PM2
Note: W means write only.
2 w
1 w
0 w
w
Bit 0 = 0 Bit 1 = 0 Bit 2 = 0 Bit 3 = 0
RB.0 works as output pin; Bit 0 = 1 RB.1 works as output pin; Bit 1 = 1 RB.2 works as output pin; Bit 2 = 1 RB.3 works as output pin; Bit 3 = 1
RB.0 works as input pin RB.1 works as input pin RB.2 works as input pin RB.3 works as input pin
At initial reset, the port RB is input mode (PM2 = 1111B). 6.17.4 Port Mode 5 Register (PM5) The port mode 5 register is organized as a 4-bit binary register (PM5.0 to PM5.3). PM5 can be used to control the input/output mode of port RD. PM5 is controlled by the MOV PM5, #I instruction. The bit descriptions are as follows: 3 PM5
Note: W means write only.
2 w
1 w
0 w
w
Bit 0 = 0 Bit 1 = 0 Bit 2 = 0 Bit 3 = 0
RD.0 works as output pin; Bit 0 = 1 RD.1 works as output pin; Bit 1 = 1 RD.2 works as output pin; Bit 2 = 1 RD.3 works as output pin; Bit 3 = 1
RD.0 works as input pin RD.1 works as input pin RD.2 works as input pin RD.3 works as input pin
At initial reset, the port RD is input mode (PM5 = 1111B).
6.18 Input Ports RC
Port RC consists of pins RC.0 to RC.3. Each pin of port RC can be connected to a pull-up resistor, which is controlled by the port mode 0 register(PM0). When the PEF, HEF, and IEF corresponding to the RC port are set, a signal change at the specified pins of port RC will execute the hold mode release or interrupt subroutine. Port status register 0 (PSR0) records the status of ports RC, i.e., any signal changes on the pins that make up the ports. PSR0 can be read out and cleared by the MOV R, PSR0, and CLR PSR0 instructions. In addition, the falling edge signal on the pin of port RC specified by the instruction MOV SEF, #I will cause the device to exit the stop mode. Refer to Figure 6-12 and the instruction table for more details.
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
DATA BUS PM0.2 Signal change detector PEF.0 D Q ck R PSR0.0
RC.0
HEF.2 PM0.2 Signal change detector PEF.1 D Q ck R PSR0.1 D ck R IEF.2 Q EVF.2
HCF.2
RC.1
INT 2
PM0.2 Signal change detector PEF.2 D Q ck R PSR0.2
RC.2
CLR EVF, #I Reset
PM0.2 Signal change detector
PEF.3 D Q ck R PSR0.3
RC.3
SEF.0 Falling Edge detector SEF.1 Falling Edge detector SEF.2 Falling Edge detector SEF.3 Falling Edge detector
Reset MOV PEF, #I CLR PSR0
To Wake Up Stop Mode
Figure 6-12 Architecture of Input Ports RC
6.18.1 Port Status Register 0 (PSR0) Port status register 0 is organized as a 4-bit binary register (PSR0.0 to PSR0.3). PSR0 can be read or cleared by the MOVA R, PSR0, and CLR PSR0 instructions. The bit descriptions are as follows: 3 PSR0
Note: R means read only.
2 R
1 R
0 R
R
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Preliminary W742C810
Bit 0 = 1 Bit 1 = 1 Bit 2 = 1 Bit 3 = 1 Signal change at RC.0 Signal change at RC.1 Signal change at RC.2 Signal change at RC.3
6.19 Output Port RE & RF
Output port RE is used as an output of the internal RT port. When the MOV RE, R instruction is executed, the data in the RAM will be output to port RT through port RE. It provides a high sink current to drive an LED. RF port is just used as an output port. When the MOV RF, R instruction is executed, the data in the RAM will be output to RF.
6.20 DTMF Output Pin (DTMF)
This pin should output the dual tone multi-frequency signal from the DTMF generator. There is a DTMF register that can specify the wanted low/high frequency, and the Dual Tone Control Register (DTCR) can control whether the dual tone will be output or not. The tones are divided into two groups (low group and high group); one tone from each group is selected to represent a digit. The relation between the DTMF signal and the corresponding touch tone keypad is shown in Figure 6-13.
C1 R1 1
C2
C3
C4
2
3
A
Row/Col R1 R2
Frequency 697 Hz 770 Hz 852 Hz 941 Hz 1209 Hz 1336 Hz 1477 Hz 1633 Hz
R2 R3
4 7
5
6
B
R3 R4 C1 C2 C3
8
9
C
R4
*
0
#
D
C4
Figure 6-13 The relation between the touch tone keypad and the frequency
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
6.20.1 DTMF register DTMF register is organized as a 4-bit binary register. By controlling the DTMF register, one tone of the low/high group can be selected. The MOV DTMF,R instruction can specify the wanted tones. The bit descriptions are as follows: 3 DTMF
Note: W means write only.
2 W
1 W
0 W
W
b3 High group X X X X Low group 0 0 1 1
Note: X means this bit do not care.
b2 X X X X 0 1 0 1
b1 0 0 1 1 X X X X
b0 0 1 0 1 X X X X
Selected tone 1209 Hz 1336 Hz 1477 Hz 1633 Hz 697 Hz 770 Hz 852 Hz 941 Hz
6.20.2 Dual Tone Control Register (DTCR) Dual tone control register is organized as a 4-bit binary register. The output of the dual or single tone will be controlled by this register. The MOV DTCR,#I instruction can specify the wanted status. The bit descriptions are as follows: 3 DTCR
Note: W means write only.
2 W
1 W
0 W
Bit 0 = 1 Bit 1 = 1 Bit 2 = 1
Low group tone output is enabled. High group tone output is enabled. DTMF output is enabled. When Bit 2 is reset to 0, the DTMF output pin will be Hi-Z state.
Bit 3 is reserved.
6.21 MFP Output Pin (MFP)
The MFP output pin can output the Timer 1 clock or the modulation frequency; the output of the pin is determined by mode register 1 (MR1). The organization of MR1 is shown in Figuer 6-7. When bit 2 of MR1 is reset to "0," the MFP output can deliver a modulation output in any combination of one signal from among DC, 4096Hz, 2048Hz, and one or more signals from among 128 Hz, 64 Hz, 8 Hz, 4 Hz, 2 Hz, or 1 Hz (when using a 32.768 KHz crystal). The MOV MFP, #I instruction is used to specify the modulation output combination. The data specified by the 8-bit operand and the MFP output pin are shown on the next page. - 28 -
Preliminary W742C810
Table 4 The relation between the MFP output frequncy and the data specified by 8-bit operand
(Fosc = 32.768 KHz)
R7 R6
R5 0 0 0
R4 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0
R3 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0
R2 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0
R1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0
R0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0
FUNCTION Low level 128 Hz 64 Hz 8 Hz 4 Hz 2 Hz 1 Hz High level 128 Hz 64 Hz 8 Hz 4 Hz 2 Hz 1 Hz 2048 Hz 2048 Hz * 128 Hz 2048 Hz * 64 Hz 2048 Hz * 8 Hz 2048 Hz * 4 Hz 2048 Hz * 2 Hz 2048 Hz * 1 Hz 4096 Hz 4096 Hz * 128 Hz 4096 Hz * 64 Hz 4096 Hz * 8 Hz 4096 Hz * 4 Hz 4096 Hz * 2 Hz 4096 Hz * 1 Hz
00
0 0 0 1 0 0 0
01
0 0 0 1 0 0 0
10
0 0 0 1 0 0 0
11
0 0 0 1
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
6.22 LCD Controller/Driver
The W742C810 can directly drive an LCD with 40 segment output pins and 4 common output pins for a total of 40 x 4 dots. The LCD driving mode is 1/3 bias 1/4 duty. The alternating frequency of the LCD can be set as Fw/64, Fw/128, Fw/256, or Fw/512. The structure of the LCD alternating frequency (FLCD) is shown in Figure 6-14.
Fw
Sub-oscillator clock
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Fw/64 Fw/128 Fw/256 Fw/512
Selector
FLCD
Figure 6-14 LCD alternating frequency (FLCD) circuit diagram
Fw = 32.768 KHz, the LCD frequency is as shown in the table below. Table 5 The relartionship between the FLCD and the duty cycle LCD Frequency 1/4 duty Fw/512 (64 Hz) 16 Hz Fw/256 (128Hz) 32 Hz Fw/128 (256 Hz) 64 Hz Fw/64 (512 Hz) 128 Hz
Corresponding to the 40 LCD drive output pins, there are 40 LCD data RAM segments. Instructions such as MOV LPL,R, MOV LPH,R, MOV @LP,R, and MOV R,@LP are used to control the LCD data RAM. The data in the LCD data RAM are transferred to the segment output pins automatically without program control. When the bit value of the LCD data RAM is "1," the LCD is turned on. When the bit value of the LCD data RAM is "0," LCD is turned off. The contents of the LCD data RAM (LCDR) are sent out through the segment0 to segment39 pins by a direct memory access. The relation between the LCD data RAM and segment/common pins is shown below. Table 6 The relation between the LCDR and segment/common pins used as LCD drive output pins COM3 LCD DATA RAM LCDR00 LCDR01 : : LCDR26 LCDR27 OUTPUT PIN SEG0 SEG1 : : SEG38 SEG39 BIT 3 0/1 0/1 : : 0/1 0/1 COM2 BIT 2 0/1 0/1 : : 0/1 0/1 COM1 BIT 1 0/1 0/1 : : 0/1 0/1 COM0 BIT 0 0/1 0/1 : : 0/1 0/1
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Preliminary W742C810
The LCDON instruction turns on the LCD display (even in HOLD mode), and the LCDOFF instruction turns off the LCD display. At initial reset, all the LCD segments are unlit. When the initial reset state ends, the LCD display is turned off automatically. To turn on the LCD display, the instruction LCDON must be executed. 6.22.1 LCD RAM addressing method There are 40 LCD RAMs (LCDR00 - LCDR27) that should be indirectly addressed. The LCD RAM pointer (LP) is used to point to the address of the wanted LCD RAM. The LP is organized as 6-bit binary register. The MOV LPL,R and MOV LPH,R instructions can load the LCD RAM address to the LP from R. The MOV @LP,R and MOV R,@LP instructions can access the pointed LCD RAM content. 6.22.2 The output waveforms for the LCD driving mode 1/3 bias 1/4 duty Lighting System (Example) Normal Operating Mode
COM0
VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS
VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS VDD VDD2 VDD1 VSS
COM1
COM2
COM3
LCD driver outputs for only seg. on COM0 side being lit LCD driver outputs for only seg. on COM1 side being lit
VDD VDD2 VDD1 VSS
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Preliminary W742C810
Continued
LCD driver outputs for seg. on COM0, COM1 sides being lit LCD driver outputs for seg. on COM1, COM2,3 sides being lit
VDD2 VDD1 VSS
VDD VDD2 VDD1 VSS
LCD driver outputs for seg. on COM1 COM2 sides being lit LCD driver outputs for seg. on COM0 COM2,3 sides being lit LCD driver outputs for seg. on COM0 COM1,2,3 sides being lit
VDD VDD2 VDD1 VSS
VDD VDD2 VDD1 VSS
VDD VDD2 VDD1 VSS
The power connections for the 1/3 bias 1/4 duty LCD driving mode are shown below.
1/3 Bias at VDD = 3.0 V
DH1 0.1uF DH2 VSS C H I P VDD = 3.0 V VDD VDD1 VDD2 0.1uF
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Preliminary W742C810
7. ABSOLUTE MAXIMUM RATINGS
PARAMETER Supply Voltage to Ground Potential Applied Input/Output Voltage Power Dissipation Ambient Operating Temperature Storage Temperature RATING -0.3 to +7.0 -0.3 to +7.0 120 0 to +70 -55 to +150 UNIT V V mW C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
8. DC CHARACTERISTICS
(VDD-VSS = 3.0 V, Fm = 3.58 MHz, Fs = 32.768 KHz, TA = 25 C, LCD on; unless otherwise specified)
PARAMETER Op. Voltage Op. Current (Crystal type)
SYM. VDD IOP1
CONDITIONS No load (Ext-V) In dual-clock normal operation
MIN. 2.4 -
TYP. 0.7
MAX. 3.6 1.0
UNIT V mA
Op. Current (Crystal type)
IOP3
No load (Ext-V) In dual-clock slow operation and when Fm is stopped 20 30 A
Hold Current (Crystal type)
IHM1
Hold mode No load (Ext-V) In dual-clock normal operation
-
-
450
A
Hold Current (Crystal type)
IHM3
Hold mode No load (Ext-V) In dual-clock slow operation and when Fm is stopped
-
15
30
A
Stop Current (Crystal type)
ISM1
Stop mode No load (Ext-V) In dual-clock normal operation
-
-
6
A
Input Low Voltage Input High Voltage
VIL VIH
-
VSS 0.7 VDD
-
0.3 VDD VDD
V V
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
DC Characteristics, continued
PARAMETER MFP Output Low Voltage MFP Output High Voltage Port RA, RB, RD and RF Output Low Voltage Port RA, RB, RD and RF Output high Voltage LCD Supply Current SEG0-SEG39 Sink Current (Used as LCD output) SEG0-SEG39 Drive Current (Used as LCD output) Port RE Sink Current Port RE Source Current DTMF Output DC level DTMF Distortion DTMF Output Voltage Pre-emphasis DTMF Output Sink Current Pull-up Resistor RES Pull-up Resistor
SYM. VML VMH VABL VABH ILCD IOL1 IOH1
CONDITIONS IOL = 3.5 mA IOH = 3.5 mA IOL = 2.0 mA IOH = 2.0 mA All Seg. ON VOL = 0.4V VLCD = 0.0V VOH = 2.4V VLCD = 3.0V VOL = 0.9V VOH = 2.4V RL = 5K, VDD = 2.5 to 3.8V RL = 5K, VDD = 2.5 to 3.8V Low group, RL = 5K Col/Row VTO = 0.5V Port RC -
MIN. 2.4 2.4 90 90
TYP. -
MAX. 0.4 0.4 6 -
UNIT V V V V A A A
IEL IEH VTDC THD VTO
9 0.4 1.1 130 1 0.2 100 20
1.2 -30 150 2 350 100
2.8 -23 170 3 1000 500
mA mA V dB mVrms dB mA K K
ITL RC RRES
9. AC CHARACTERISTICS
PARAMETER Op. Frequency Instruction cycle time Reset Active Width Interrupt Active Width SYM. FOSC TI TRAW TIAW CONDITIONS Crystal type One machine cycle FOSC = 32.768 KHz FOSC = 32.768 KHz MIN. 1 1 TYP. 3.58 4/FOSC MAX. UNIT MHz S S S
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Preliminary W742C810
10. INSTRUCTION SET TABLE
Symbol Description ACC: ACC.n: WR: WRP: PAGE: DBKR: ROMPR: MR0: MR1: PM0: PM1: PM2: PM5: PSR0: R: LP: LPL: LPH: R.n: I: L: CF: ZF: PC: TM0L: TM0H: TM1L: TM1H: TAB0: TAB1: TAB2: TAB3: IEF.n: Accumulator Accumulator bit n Working Register WR Page register Page Register Data Bank Register ROM Page Register Mode Register 0 Mode Register 1 Port Mode 0 Port Mode 1 Port Mode 2 Port Mode 5 Port Status Register 0 Memory (RAM) of address R LCD data RAM pointer Low nibble of the LCD data RAM pointer High nibble of the LCD data RAM pointer Memory bit n of address R Constant parameter Branch or jump address Carry Flag Zero Flag Program Counter Low nibble of the Timer 0 counter High nibble of the Timer 0 counter Low nibble of the Timer 1 counter High nibble of the Timer 1 counter Look-up table address buffer 0 Look-up table address buffer 1 Look-up table address buffer 2 Look-up table address buffer 3 Interrupt Enable Flag n
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
Instruction Set Table, continued
HCF.n: HEF.n: SEF.n: PEF.n: EVF.n: DTMF: DTCR: ! =: &: ^: EX: : [PAGE*10H+()]: [P()]:
Machine code Arithmetic 0001 1000 0xxx xxxx 0001 1100 i i i i nnnn 0001 1001 0xxx xxxx 0001 1101 i i i i nnnn 0000 1000 0xxx xxxx 0000 1100 i i i i nnnn 0000 1001 0xxx xxxx 0000 1101 i i i i nnnn 0010 1000 0xxx xxxx 0010 1100 i i i i nnnn 0010 1001 0xxx xxxx 0010 1101 i i i i nnnn 0001 1010 0xxx xxxx 0001 1110 i i i i nnnn 0001 1011 0xxx xxxx 0001 1111 i i i i nnnn 0000 1010 0xxx xxxx 0000 1110 i i i i nnnn 0000 1011 0xxxxxxx
HOLD mode release Condition Flag n HOLD mode release Enable Flag n STOP mode wake-up Enable Flag n Port Enable Flag n Event Flag n DTMF Register DTMF Control Register Not equal AND OR Exclusive OR Transfer direction, result Contents of address PAGE(bit2, bit1, bit0)*10H+() Contents of port P
Mnemonic ADD ADD ADDR ADDR ADC ADC ADCR ADCR ADU ADU ADUR ADUR SUB SUB SUBR SUBR SBC SBC SBCR R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC Function Flag affected ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF ZF ZF ZF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF ZF, CF W/C 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1
ACC(R) + (ACC) ACC(WRn) + I ACC, R(R) + (ACC) ACC, WRn(WRn) + I ACC(R) + (ACC) + (CF) ACC(WRn) + I + (CF) ACC, R(R) + (ACC) + (CF) ACC, WRn(WRn) + I + (CF) ACC(R) + (ACC) ACC(WRn) + I ACC, R(R) + (ACC) ACC, WRn(WRn) + I ACC(R) - (ACC) ACC(WRn) - I ACC, R(R) - (ACC) ACC, WR(WR) - I ACC(R) - (ACC) - (CF) ACC(WRn) - I - (CF) ACC, R(R) - (ACC) - (CF)
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Preliminary W742C810
Instruction set, continued Machine code 0000 1111 i i i i nnnn 0100 1010 0xxx xxxx 0100 1010 1xxx xxxx Logic 0010 1010 0xxx xxxx 0010 1110 i i i i nnnn 0010 1011 0xxx xxxx 0010 1111 i i i i nnnn 0011 1010 0xxx xxxx 0011 1110 i i i i nnnn 0011 1011 0xxx xxxx 0011 1111 i i i i nnnn 0011 1000 0xxx xxxx 0011 1100 i i i i nnnn 0011 1001 0xxx xxxx 0011 1101 i i i i nnnn Branch 0111 0aaa aaaa aaaa 1000 0aaa aaaa aaaa 1001 0aaa aaaa aaaa 1010 0aaa aaaa aaaa 1011 0aaa aaaa aaaa 1110 0aaa aaaa aaaa 1100 0aaa aaaa aaaa 1111 0aaa aaaa aaaa 1101 0aaa aaaa aaaa 0100 1000 0xxx xxxx 0100 1000 1xxx xxxx 1010 1000 0xxx xxxx 1010 1000 1xxx xxxx 1010 1001 0xxx xxxx 1010 1001 1xxx xxxx Subroutine 0110 0aaa aaaa aaaa CALL L STACK (PC)+1; PC12 ~ PC0 (ROMPR)x800H+L10 ~ L0 0000 0001 0000 0000 RTN (PC) STACK 1/1 1/1 JMP JB0 JB1 JB2 JB3 JZ JNZ JC JNC DSKZ DSKNZ SKB0 SKB1 SKB2 SKB3 L L L L L L L L L R R R R R R PC12~PC0(ROMPR)x800H+L10~L0 PC10~PC0L10~L0; if ACC.0 = "1" PC10~PC0L10~L0; if ACC.1 = "1" PC10~PC0L10~L0; if ACC.2 = "1" PC10~PC0L10~L0; if ACC.3 = "1" PC10~PC0L10~L0; if ACC = 0 PC10~PC0L10~L0; if ACC ! = 0 PC10~PC0L10~L0; if CF = "1" PC10~PC0L10~L0; if CF != "1" ACC, R(R) - 1; PC (PC) + 2 if ACC = 0 ACC, R(R) - 1; PC (PC) + 2 if ACC != 0 PC (PC) + 2 if R.0 = "1" PC (PC) + 2 if R.1 = "1" PC (PC) + 2 if R.2 = "1" PC (PC) + 2 if R.3 = "1" ZF, CF ZF, CF 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 ANL ANL ANLR ANLR ORL ORL ORLR ORLR XRL XRL XRLR XRLR R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I R, ACC WRn, #I ACC(R) & (ACC) ACC(WRn) & I ACC, R(R) & (ACC) ACC, WRn(WRn) & I ACC(R) (ACC) ACC(WRn) I ACC, R(R) (ACC) ACC, WRn(WRn) I ACC(R) EX (ACC) ACC(WRn) EX I ACC, R(R) EX (ACC) ACC, WRn(WRn) EX I ZF ZF ZF ZF ZF ZF ZF ZF ZF ZF ZF ZF 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 Mnemonic SBCR INC DEC WRn, #I R R Function ACC, WRn(WRn) - I - (CF) ACC, R(R) + 1 ACC, R(R) - 1 Flag affected ZF, CF ZF, CF ZF, CF W/C 1/1 1/1 1/1
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
Instruction set, continued Machine code Data move 1110 1nnn nxxx xxxx 1111 1nnn nxxx xxxx 0110 1nnn nxxx xxxx 0111 1nnn nxxx xxxx 0101 1001 1xxx xxxx 0100 1110 1xxx xxxx 1011 1 i i i i xxx xxxx 1100 1nnn n000 qqqq 1101 1nnn n000 qqqq 1000 1100 0xxx xxxx 1000 1100 1xxx xxxx 1000 1110 0xxx xxxx 1000 1110 1xxx xxxx 1000 1101 0xxx xxxx Input & Output 0101 1011 0xxx xxxx 0101 1011 1xxx xxxx 0100 1011 0xxx xxxx 0100 1011 1xxx xxxx 0101 1010 0xxx xxxx 0101 1010 1xxx xxxx 1010 1100 1xxx xxxx 0101 1110 0xxx xxxx 1010 1110 0xxx xxxx 0001 0010 i i i i i i i i Flag & Register 0101 1111 1xxx xxxx 0101 1110 1xxx xxxx 0101 0110 1000 0i i i 1001 1101 1xxx xxxx 1001 1100 1xxx xxxx 0011 0101 1000 i i i i MOVA MOV MOV MOV MOV MOV R, PAGE PAGE, R PAGE, #I R, WRP WRP, R WRP, #I ACC, RPAGE (Page Register) PAGE(R) PAGEI RWRP WRP(R) WRPI ZF 1/1 1/1 1/1 1/1 1/1 1/1 MOVA MOVA MOVA MOVA MOV MOV MOV MOV MOV MOV R, RA R, RB R, RC R, RD RA, R RB, R RD, R RE, R RF, R MFP, #I ACC, R[RA] ACC, R[RB] ACC, R[RC] ACC, R[RD] [RA](R) [RB](R) [RD](R) [RE](R) [RF](R) [MFP] I ZF ZF ZF ZF 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 MOV MOV MOVA MOVA MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVC WRn, R R, WRn WRn, R R, WRn R, ACC ACC, R R, #I WRn, @WRq @WRq, WRn TAB0, R TAB1, R TAB2, R TAB3, R R WRn(R) R(WRn) ACC, WRn(R) ACC, R(WRn) R(ACC) ACC(R) RI WRn[(DBKR)x80H+(PAGE)x10H +(WRq)] [(DBKR)x80H+(PAGE)x10H +(WRq)]WRn TAB0(R) TAB1(R) TAB2(R) TAB3(R) R[(TAB3)x1000H+(TAB2)x100H+(TAB1) x10H + (TAB0)] ZF ZF ZF 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/2 1/2 1/1 1/1 1/1 1/1 1/2 Mnemonic Function Flag affected W/C
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Preliminary W742C810
Instruction set, continued Machine code 1001 1101 0000nnnn 1001 1100 0000nnnn 0011 0101 0000 0i i i 0011 0100 0000 00i i 1000 1000 0xxx xxxx 1000 1001 0xxx xxxx 0001 0011 1000 i 0 0 i 0001 0011 0000 i i i i 0101 1001 0xxx xxxx 0101 1000 0xxx xxxx 0100 1001 0xxx xxxx 0100 1001 1xxx xxxx 0101 0011 0000 i i i i 0101 0111 0000 i i i i 0101 0111 1000 i i i i 0011 0111 1000 i i i i 0100 0000 i 0 0 i 0i i i 0100 0001 i 0 0 i 0 i i i 0101 0001 i 0 0 i 0i i i 0100 0011 0000 i i i i 0101 0010 0000 i i i i 0101 0100 0000 i i i i 0100 1111 0xxx xxxx 0100 0010 0000 0000 0101 0000 0100 0000 0101 0000 0000 0000 0001 0111 0000 0000 0101 0101 1000 0000 0001 0111 1000 0000 Shift & Rotate 0100 1101 0xxx xxxx SHRC R ACC.n, R.n(R.n+1); ACC.3, R.30; CFR.0 ZF, CF 1/1 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOVA MOV MOVA MOVA MOV MOV MOV MOV CLR MOV MOV MOV MOV MOV MOVA CLR SET CLR CLR CLR CLR WRn,DBKR DBKR, WRn DBKR, #I ROMPR, #I ROMPR, R R, ROMPR MR0, #I MR1, #I R, CF CF, R R, HCFL R, HCFH PM0, #I PM1, #I PM2, #I PM5, #I EVF, #I HEF, #I IEF, #I PEF, #I SEF, #I SCR, #I R, PSR0 PSR0 CF CF DIVR0 DIVR1 WDT Function WRnDBKR DBKRWRn DBKRI ROMPRI ROMPR(R) R(ROMPR) MR0I MR1I ACC.0, R.0CF CF(R.0) ACC, RHCF.0~HCF.3 ACC, RHCF.4~HCF.7 Port Mode 0 I Port Mode 1 I Port Mode 2 I Port Mode 5 I Clear Event Flag if In = 1 Set/Reset HOLD mode release Enable Flag Set/Reset Interrupt Enable Flag Set/Reset Port Enable Flag Set/Reset STOP mode wake-up Enable Flag for RC port SCRI ACC, RPort Status Register 0 Clear Port Status Register 0 Set Carry Flag Clear Carry Flag Clear the last 4-bit of the Divider 0 Clear the last 4-bit of the Divider 1 Clear WatchDog Timer CF CF ZF ZF CF ZF ZF Flag affected W/C 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1 1/1
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
Instruction set, continued Machine code 0100 1101 1xxx xxxx Mnemonic RRC R Function ACC.n, R.n(R.n+1); ACC.3, R.3CF; CFR.0 0100 1100 0xxx xxxx SHLC R ACC.n, R.n(R.n-1); ACC.0, R.00; CFR.3 0100 1100 1xxx xxxx RLC R ACC.n, R.n(R.n-1); ACC.0, R.0CF; CFR.3 LCD 1001 1000 0xxx xxxx 1001 1000 1xxx xxxx 1001 1010 0xxx xxxx 1001 1011 0xxx xxxx 0000 0010 0000 0000 0000 0010 1000 0000 DTMF 1001 1110 1xxx xxxx 0011 0100 1000 0 i i i Timer 1010 1010 0xxx xxxx 1010 1010 1xxx xxxx 1010 1011 0xxx xxxx 1010 1011 1xxx xxxx Other 0000 0000 1000 0000 0000 0000 1100 0000 0000 0000 0000 0000 0101 0000 1100 0000 0101 0000 1000 0000 HOLD STOP NOP EN DIS INT INT Enter Hold mode Enter Stop mode No operation Enable interrupt function Disable interrupt function 1/1 1/1 1/1 1/1 1/1 MOV MOV MOV MOV TM0L, R TM0H, R TM1L, R TM1H, R TM0L(R) TM0H(R) TM1L(R) TM1H(R) 1/1 1/1 1/1 1/1 MOV MOV DTMF, R DTCR, #I DTMF(R) DTCR I 1/1 1/1 MOV MOV MOV MOV LCDON LCDOFF LPL, R LPH, R @LP, R R, @LP LPL(R) LPH(R) [(LPH)x10H+(LPL)](R) R[(LPH) x10H+(LPL)] LCD ON LCD OFF 1/1 1/1 1/1 1/1 1/1 1/1 ZF, CF 1/1 ZF, CF 1/1 Flag affected ZF, CF W/C 1/1
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Preliminary W742C810
11. PACKAGE DIMENSIONS
100-pin QFP
HD D
E
HE
e
b
c
A2 A See Detail F Seating Plane A1 y L L1
Controlling dimension: Millimeters
Dimension in inches Dimension in mm Min. Nom. Max.
Symbol
Min.
Nom.
Max.
A A1 A2 b c D E e HD HE L L1 y
0.010 0.014 0.101 0.107 0.008 0.012 0.004 0.006 0.547 0.551 0.783 0.787 0.020 0.026 0.746 0.960 0.039 0.740 0.976 0.047 0.064
0.018 0.113 0.016 0.008
0.25 2.57 0.20 0.10
0.35 2.72 0.30 0.15
0.45 2.87 0.40 0.20
0.555 13.90 0.791 19.90 0.032
14.00 14.10 20.00 20.10 0.802
0.498 0.65
0.756 18.40 0.992 24.40 0.055 1.00
18.80 19.20 24.80 25.20 1.20 2.40 1.40
0.003 0 7 0
0.08 7
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Publication Release Date: May 1999 Revision A1
Preliminary W742C810
Headquarters
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, No. 4, Creation Rd. III, 123 Hoi Bun Rd., Kwun Tong, Science-Based Industrial Park, Kowloon, Hong Kong Hsinchu, Taiwan TEL: 852-27513100 TEL: 886-3-5770066 FAX: 852-27552064 FAX: 886-3-5792766 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-27197006
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2727 N. First Street, San Jose, CA 95134, U.S.A. TEL: 408-9436666 FAX: 408-5441798
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-27190505 FAX: 886-2-27197502
Note: All data and specifications are subject to change without notice.
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